Power dissipation in high performance microprocessors continue to increase due to the use of parallel architectures, larger on-die cache memories, and increasing clock frequencies. Parallel architectures may include processor core designs that permit multiple operations running at the same time or multiple cores on the same die. Scaling the power supply voltage (Vcc) in accordance with changing process technology is a typical method to improve performance while staying within a power envelope.
Power supply voltage scaling, however, may have significant design implications. For example, lower Vcc levels reduce the circuit design voltage headroom. Therefore, a Vcc droop that is transient in nature may reduce the circuit operating speed or even result in circuit failures. Voltage droop may be caused by power delivery inductive noise generated by an increase in microprocessor activities.
In order to mitigate the effects of Vcc droop, on-die power supply de-coupling and on-die Vcc filtering techniques are often used. However, on-die de-coupling using conventional MOS gate capacitors is becoming increasingly impractical due to the high MOS gate leakage. Low leakage on-die capacitors are typically area intensive and inefficient. On-die Vcc filtering can typically only be applied to a limited number of devices due to the additional voltage drop and leakage. Moreover, since on-die capacitors are needed for the Vcc filters, this technique suffers the same drawback as on-die Vcc de-coupling due to the on-die capacitor constraints.